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ADE7858ACPZ 数据表(PDF) 63 Page - Analog Devices

部件名 ADE7858ACPZ
功能描述  Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers
PDF  76 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7858ACPZ 数据表(HTML) 63 Page - Analog Devices

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Preliminary Technical Data
ADE7858
Rev. PrA | Page 63 of 76
Table 25. HPFDIS register (address 0x43B6)
Bit
Location
Bit
Mnemonic
Default
value
Description
23:0
00000000
When HPFDIS=0x00000000, then all high pass filters in voltage and current channels are enabled.
When the register is set to any non zero value, all high pass filters are disabled.
Table 26. IPEAK register (address 0xE500)
Bit Location
Bit Mnemonic
Default value
Description
23-0
IPEAKVAL[23:0]
0
These bits contain the peak value determined in the current channel.
24
IPPHASE[0]
0
When this bit is set to 1, phase A current generated IPEAKVAL[23:0] value.
25
IPPHASE[1]
0
When this bit is set to 1, phase B current generated IPEAKVAL[23:0] value.
26
IPPHASE[2]
0
When this bit is set to 1, phase C current generated IPEAKVAL[23:0] value.
31-27
00000
These bits are always 0.
Table 27. VPEAK register (address 0xE501)
Bit Location
Bit Mnemonic
Default value
Description
23-0
VPEAKVAL[23:0]
0
These bits contain the peak value determined in the voltage channel.
24
VPPHASE[0]
0
When this bit is set to 1, phase A voltage generated VPEAKVAL[23:0] value.
25
VPPHASE[1]
0
When this bit is set to 1, phase B voltage generated VPEAKVAL[23:0] value.
26
VPPHASE[2]
0
When this bit is set to 1, phase C voltage generated VPEAKVAL[23:0] value.
31-27
00000
These bits are always 0.
Table 28. STATUS0 register (address 0xE502)
Bit
Location
Bit
Mnemonic
Default
value
Description
0
AEHF
0
When this bit is set to 1, it indicates that bit 30 of any one of the total active energy registers
AWATTHR, BWATTHR, CWATTHR has changed.
1
Reserved
0
This bit is always set to 0.
2
REHF
0
When this bit is set to 1, it indicates that bit 30 of any one of the total reactive energy registers
AVARHR, BVARHR, CVARHR has changed.
3
Reserved
0
This bit is always set to 0.
4
VAEHF
0
When this bit is set to 1, it indicates that bit 30 of any one of the apparent energy registers AVAHR,
BVAHR, CVAHR has changed.
5
LENERGY
0
When this bit is set to 1, in line energy accumulation mode, it indicates the end of an integration
over an integer number of half line cycles set in LINECYC[15:0] register.
6
REVAPA
0
When this bit is set to 1, it indicates that the phase A total active power has changed sign. The sign
itself is indicated in bit 0 (AWSIGN) of PHSIGN[15:0] register (see Table 38).
7
REVAPB
0
When this bit is set to 1, it indicates that the phase B total active power has changed sign. The sign
itself is indicated in bit 1 (BWSIGN) of PHSIGN[15:0] register (see Table 38).
8
REVAPC
0
When this bit is set to 1, it indicates that the phase C total active power has changed sign. The sign
itself is indicated in bit 2 (CWSIGN) of PHSIGN[15:0] register (see Table 38).
9
REVPSUM1
0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data path has
changed sign. The sign itself is indicated in bit 3 (SUM1SIGN) of PHSIGN[15:0] register (see Table 38).
10
REVRPA
0
When this bit is set to 1, it indicates that the phase A total reactive power has changed sign. The
sign itself is indicated in bit 4 (AVARSIGN) of PHSIGN[15:0] register (see Table 38).
11
REVRPB
0
When this bit is set to 1, it indicates that the phase B total reactive power has changed sign. The sign
itself is indicated in bit 5 (BVARSIGN) of PHSIGN[15:0] register (see Table 38).
12
REVRPC
0
When this bit is set to 1, it indicates that the phase C total reactive power has changed sign. The sign
itself is indicated in bit 6 (CVARSIGN) of PHSIGN[15:0] register (see Table 38).
13
REVPSUM2
0
When this bit is set to 1, it indicates that the sum of all phase powers in the CF2 data path has
changed sign. The sign itself is indicated in bit 7 (SUM2SIGN) of PHSIGN[15:0] register (see Table 38).
14
CF1
When this bit is set to 1, it indicates a high to low transition has occurred at CF1 pin, that is an active
low pulse has been generated. The bit is set even if the CF1 output is disabled by setting bit 9
(CF1DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF1 pin is determined by bits
2-0 (CF1SEL) in CFMODE[15:0] register (see Table 36).
15
CF2
When this bit is set to 1, it indicates a high to low transition has occurred at CF2 pin, that is an active



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