ADE7858ACPZ datasheet(12/76 Pages) AD

12 / 76 page

ADE7858

Preliminary Technical Data

Rev. PrA| Page 12 of 76

AGND

This pin provides the ground reference for the analog circuitry in the ADE7858. This pin

should be tied to the analog ground plane or the quietest ground reference in the system.

This quiet ground reference should be used for all analog circuitry, for example, antialiasing

filters, current, and voltage transducers.

VDD

This pin provides the supply voltage for the ADE7858. In PSM0 (normal power mode) the

supply voltage should be maintained at 3.3 V ± 10% for specified operation. In PSM1

(reduced power mode), PSM2 (low power mode) and PSM3 (sleep mode), when the

ADE7858 is supplied from a battery, the supply voltage should be maintained between 2.4

and 3.7V. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a

ceramic 100 nF capacitor.

CLKIN

Master Clock for ADE7858. An external clock can be provided at this logic input.

Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to

provide a clock source for the ADE7858. The clock frequency for specified operation is

16.384 MHz. Ceramic load capacitors of a few tens of picofarad should be used with the gate

oscillator circuit. Refer to the crystal manufacturer’s data sheet for the load capacitance

requirements.

CLKOUT

A crystal can be connected across this pin and CLKIN as previously described to provide a

clock source for the ADE7858. The CLKOUT pin can drive one CMOS load when either an

external clock is supplied at CLKIN or a crystal is being used.

29,

IRQ

Interrupt Request Outputs. These are active low logic outputs. See the

Interrupts section for a detailed presentation of the events that may trigger interrupts.

33,34,35

CF1,CF2,CF3/HSCLK

Calibration Frequency (CF) Logic Outputs. Provide power information based on CF1SEL,

CF2SEL, CF3SEL bits in CFMODE register. These outputs are used for operational and

calibration purposes. The full-scale output frequency can be scaled by writing to the

respectively CF1DEN, CF2DEN, CF3DEN registers (see the Energy to Frequency Conversion

section).CF3 is multiplexed with the serial clock output of HSDC port.

SCLK/SCL

Serial Clock Input for SPI port / Serial Clock Input for I2C port. All serial data transfers are

synchronized to this clock (see the Serial Interfaces section). This pin has a Schmidt-trigger

input for use with a clock source that has a slow edge transition time, for example, opto-

isolator outputs.

MISO/HSD

Data Out for SPI port / Data Out for HSDC port

MOSI/SDA

Data In for SPI port / Data Out for I2C port

SS /HSA

Slave Select for SPI port / HSDC port active

EPAD

Exposed Pad

The exposed pad should be connected to AGND.

ADE7858ACPZ 数据表(PDF) 12 Page - Analog Devices

ADE7858ACPZ 数据表(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载