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ADE7858ACPZ 数据表(PDF) 7 Page - Analog Devices |
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ADE7858ACPZ 数据表(HTML) 7 Page - Analog Devices |
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7 / 76 page  Preliminary Technical Data ADE7858 Rev. PrA | Page 7 of 76 TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz , TMIN to TMAX = −40°C to +85°C. Table 2. I2C Compatible Interface Timing Parameter Standard mode Fast Mode Parameter Symbol Min Max Min Max Unit SCL clock frequency fSCL 0 100 0 400 kHz Hold time (repeated) START condition. tHD;STA 4.0 0.6 μs LOW period of SCL clock tLOW 4.7 1.3 μs HIGH period of SCL clock tHIGH 4.0 0.6 μs Set-up time for a repeated START condition tSU;STA 4.7 0.6 μs Data hold time tHD;DAT 0 3.45 0 0.9 μs Data setup time tSU;DAT 250 100 ns Rise time of both SDA and SCL signals tr 1000 20 300 ns Fall time of both SDA and SCL signals tf 300 20 300 ns Setup time for STOP condition tSU;STO 4.0 0.6 μs Bus free time between a STOP and START condition tBUF 4.7 1.3 μs Pulse width of suppressed spikes tSP na 50 ns SDA SCLK t f START CONDITION START CONDITION STOP CONDITION t LOW t r t SU;DAT t f t HD;STA t BUF t r t SU;STO t SU;STA t HIGH t HD;DAT t HD;STA REPEATED START CONDITION t SP Figure 2. I2C Compatible Interface Timing |
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