ADE7858ACPZ datasheet(64/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 64 of 76

Bit

Location

Bit

Mnemonic

Default

value

Description

low pulse has been generated. The bit is set even if the CF2 output is disabled by setting bit 10

(CF2DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF2 pin is determined by bits

5-3 (CF2SEL) in CFMODE[15:0] register (see Table 36).

CF3

When this bit is set to 1, it indicates a high to low transition has occurred at CF3 pin, that is an active

low pulse has been generated. The bit is set even if the CF3 output is disabled by setting bit 11

(CF3DIS) to 1 in CFMODE[15:0] register. The type of the powers used at CF3 pin is determined by bits

8-6 (CF3SEL) in CFMODE[15:0] register (see Table 36).

DREADY

When this bit is set to 1, it indicates that all periodical (at 8KHz rate) DSP computations have

finished.

REVPSUM3

When this bit is set to 1, it indicates that the sum of all phase powers in the CF3 data path has

changed sign. The sign itself is indicated in bit 8 (SUM3SIGN) of PHSIGN[15:0] register (see Table 38).

31-19

Reserved

0 0000

0000

Reserved. These bits are always 0.

Table 29. STATUS1 register (address 0xE503)

Bit

Location

Bit

Mnemonic

Default

value

Description

NLOAD

When this bit is set to 1, it indicates that at least one phase entered no-load condition based on total

active and reactive powers. The phase is indicated in bits 2-0 (NLPHASE) in PHNOLOAD[15:0] register

(see Table 33).

Reserved

This bit is always set to 0.

VANLOAD

When this bit is set to 1, it indicates that at least one phase entered no-load condition based on

apparent power. The phase is indicated in bits 8-6 (VANLPHASE) in PHNOLOAD[15:0] register (see

Table 33).

ZXTOVA

When this bit is set to 1, it indicates a zero crossing on phase A voltage is missing.

ZXTOVB

When this bit is set to 1, it indicates a zero crossing on phase B voltage is missing.

ZXTOVC

When this bit is set to 1, it indicates a zero crossing on phase C voltage is missing.

ZXTOIA

When this bit is set to 1, it indicates a zero crossing on phase A current is missing.

ZXTOIB

When this bit is set to 1, it indicates a zero crossing on phase B current is missing.

ZXTOIC

When this bit is set to 1, it indicates a zero crossing on phase C current is missing.

ZXVA

When this bit is set to 1, it indicates a zero crossing has been detected on phase A voltage.

ZXVB

When this bit is set to 1, it indicates a zero crossing has been detected on phase B voltage.

ZXVC

When this bit is set to 1, it indicates a zero crossing has been detected on phase C voltage.

ZXIA

When this bit is set to 1, it indicates a zero crossing has been detected on phase A current.

ZXIB

When this bit is set to 1, it indicates a zero crossing has been detected on phase B current.

ZXIC

When this bit is set to 1, it indicates a zero crossing has been detected on phase C current.

RSTDONE

In case of a software reset command, bit 7 (SWRST) set to 1 in CONFIG[15:0] register, or a transition

from PSM1, PSM2 or PSM3 to PSM0, or a hardware reset, this bit is set to 1 at the end of the transition

process and after all registers changed value to default.

IRQ pin goes low to signal this moment

because this interrupt cannot be disabled.

SAG

When this bit is set to 1, it indicates a SAG event has occurred on one of the phases indicated by bits

14-12 (VSPHASE) in PHSTATUS[15:0] register (see Table 32).

When this bit is set to 1, it indicates an overcurrent event has occurred on one of the phases

indicated by bits 5-3 (OIPHASE) in PHSTATUS[15:0] register (see Table 32).

When this bit is set to 1, it indicates an overvoltage event has occurred on one of the phases

indicated by bits 11-9 (OVPHASE) in PHSTATUS[15:0] register (see Table 32).

SEQERR

When this bit is set to 1, it indicates a negative to positive zero crossing on phase A voltage was not

followed by a negative to positive zero crossing on phase B voltage, but by a negative to positive

zero crossing on phase C voltage.

Reserved

Reserved. This bit is always set to 0.

Reserved

Reserved. This bit is always set to 1.

Reserved

Reserved. This bit is always set to 0.

PKI

When this bit is set to 1, it indicates that the period used to detect the peak value in the current

channel has ended. IPEAK[31:0] register contains the peak value and the phase where the peak has

been detected (see Table 26).

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