ADE7858ACPZ datasheet(24/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 24 of 76

The ADE7858 contains a High Speed Data Capture (HSDC)

port that is specially designed to provide fast access to the

waveform sample registers. See HSDC Interface section for

more details.

CHANGING PHASE VOLTAGE DATA PATH

The ADE7858 may direct one phase voltage input to the

computational data path of another phase. For example, phase

A voltage may be introduced in the phase B computational data

path, which means all powers computed by the ADE7858 in

phase B are based on phase A voltage and phase B current.

Bits 9-8 (VTOIA[1:0]) of CONFIG[15:0] register manage the

phase A voltage measured at VA pin. If VTOIA[1:0]=00 (default

value), the voltage is directed to phase A computational data

path, if VTOIA[1:0]=01, the voltage is directed to phase B path

and if VTOIA[1:0]=10, the voltage is directed to phase C path.

If VTOIA[1:0]=11, the ADE7858 behaves as if VTOIA[1:0]=00.

Bits 11-10 (VTOIB[1:0]) of CONFIG[15:0] register manage the

phase B voltage measured at VB pin. If VTOIB[1:0]=00 (default

value), the voltage is directed to phase B computational data

path, if VTOIB[1:0]=01, the voltage is directed to phase C path

and if VTOIB[1:0]=10, the voltage is directed to phase A path.

If VTOIB[1:0]=11, the ADE7858 behaves as if VTOIB[1:0]=00.

Bits 13-12 (VTOIC[1:0]) of CONFIG[15:0] register manage the

phase C voltage measured at VC pin. If VTOIC[1:0]=00 (default

value), the voltage is directed to phase C computational data

path, if VTOIC[1:0]=01, the voltage is directed to phase A path

and if VTOIC[1:0]=10, the voltage is directed to phase B path.

If VTOIC[1:0]=11, the ADE7858 behaves as if VTOIC[1:0]=00.

APHCAL

Phase A

Computational

data path

BPHCAL

Phase B

Computational

data path

CPHCAL

Phase C

Computational

data path

VTOIA[1:0]=01,

Phase A voltage

directed to phase B

VTOIB[1:0]=01,

Phase B voltage

directed to phase C

VTOIC[1:0]=01,

Phase C voltage

directed to phase A

Figure 23.Phase voltages used in different data paths

Figure 23 presents the case in which phase A voltage is used in

the phase B data path, phase B voltage is used in phase C data

path and phase C voltage is used in phase A data path.

POWER QUALITY MEASUREMENTS

Zero Crossing Detection

The ADE7858 has a zero-crossing (ZX) detection circuit on the

current and voltage channels. Zero-crossing events are used as a

time base for various power quality measurements and in the

calibration process.

A zero-crossing is generated from the output of LPF1. The low

pass filter is intended to eliminate all harmonics of 50Hz and

60Hz systems and help identify the zero crossing events on the

fundamental components of both current and voltage channels.

The digital filter has a pole at 80Hz and is clocked at 256KHz.

As a result, there is a phase lag between the analog input signal

(one of IA, IB, IC, VA, VB and VC) and the output of LPF1. The

error in ZX detection is 0.07° for 50Hz systems (0.085° for 60Hz

systems). The phase lag response of LPF1 results in a time delay

of approximately 31.4° or 1.74msec (@ 50 Hz) between its input

and output. The overall delay between the zero crossing on the

analog inputs and ZX detection obtained after LPF1 is around

39.6° or 2.2 msec (@ 50 Hz). The ADC and HPF introduce the

additional delay. The LPF1 cannot be disabled to assure a good

resolution of the ZX detection. Figure 24 shows how the zero-

crossing signal is detected.

PGA

ADC

REFERENCE

GAIN[23:0]

HPF

DSP

LPF1

DETECTION

IA, IB, IC

VA, VB, VC

IA, IB, IC, IN

VA, VB, VC

LPF1 output

0.855

39.6 deg or 2.2msec

@ 50Hz

HPFDIS[23:0]

Figure 24. Zero-Crossing Detection on Voltage and Current channels

In order to provide further protection from noise, input signals to

the voltage channel with amplitude lower than 10% of full scale do

not generate zero crossing events at all. The current channel ZX

detection circuit is active for all input signals independent of their

amplitude.

The ADE7858 contains six zero crossing detection circuits, one

for each phase voltage and current channel. Each circuit drives

one flag in STATUS1[31:0] register. If circuit placed in phase A

voltage channel detects one zero crossing event, then bit 9

(ZXVA) in STATUS1[31:0] register is set to 1. Similarly, phase B

voltage circuit drives bit 10 (ZXVB), phase C voltage circuit

drives bit 11 (ZXVC) and circuits placed in the current channel

drive bit 12 (ZXIA), bit 13 (ZXIB) and bit 14 (ZXIC). If a ZX

detection bit is set in the MASK1[31:0] register, the

IRQ interrupt pin is driven low and the corresponding status

flag is set to 1. The status bit is cleared and

IRQ

pin is set back

high by writing STATUS1 register with the status bit set to 1.

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