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ADE7858ACPZ 数据表(PDF) 71 Page - Analog Devices |
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ADE7858ACPZ 数据表(HTML) 71 Page - Analog Devices |
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71 / 76 page  Preliminary Technical Data ADE7858 Rev. PrA | Page 71 of 76 Bit Location Bit Mnemonic Default value Description -01: 3 phase 3 wires delta connection -10: 3 phase 4 wires with 2 voltage sensors -11: 3 phase 4 wires delta connection Energy Registers CONSEL[1:0]=00 CONSEL[1:0]=01 CONSEL[1:0]=10 CONSEL[1:0]=11 AWATTHR, AFWATTHR VA x IA VA x IA VA x IA VA x IA BWATTHR, BFWATTHR VB x IB 0 VB=-VA-VC VB x IB VB=-VA VB x IB CWATTHR, CFWATTHR VC x IC VC x IC VC x IC VC x IC AVARHR, AFVARHR VA x IA’ VA x IA’ VA x IA’ VA x IA’ BVARHR, BFVARHR VB x IB’ 0 VB=-VA-VC VB x IB’ VB=-VA VB x IB’ CVARHR, CFVARHR VC x IC’ VC x IC’ VC x IC’ VC x IC’ AVAHR VARMS x IARMS VARMS x IARMS VARMS x IARMS VARMS x IARMS BVAHR VBRMS x IBRMS 0 VBRMS x IBRMS VBRMS x IBRMS CVAHR VCRMS x ICRMS VCRMS x ICRMS VCRMS x ICRMS VCRMS x ICRMS 7,6 Reserved 00 Reserved. These bits do not manage any functionality. Table 42. LCYCMODE register (address 0xE702) Bit Location Bit Mnemonic Default value Description 0 LWATT 0 -0: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR) are placed in regular accumulation mode. -1: the watt-hour accumulation registers (AWATTHR, BWATTHR, CWATTHR) are placed into line- cycle accumulation mode. 1 LVAR 0 -0: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed in regular accumulation mode. -1: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR) are placed into line-cycle accumulation mode. 2 LVA 0 -0: the va-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed in regular accumulation mode. -1: the va-hour accumulation registers (AVAHR, BVAHR, CVAHR) are placed into line-cycle accumulation mode. 3 ZXSEL[0] 1 -0: phase A is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase A is selected for zero crossings counts in the line cycle accumulation mode. If more than one phase is selected for zero crossing detection, the accumulation time is shorten accordingly 4 ZXSEL[1] 1 -0: phase B is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase B is selected for zero crossings counts in the line cycle accumulation mode. 5 ZXSEL[2] 1 -0: phase C is not selected for zero crossings counts in the line cycle accumulation mode. -1: phase C is selected for zero crossings counts in the line cycle accumulation mode. 6 RSTREAD 1 -0: Read-with-reset of all energy registers is disabled. This bit should be cleared to 0 when bits 2,1,0 (LWATT, LVAR, LVA) are set to 1. -1: Read-with-reset of all xWATTHR, xVARHR, xVAHR registers (x=A,B,C) is enabled. This means a read of those registers resets them to 0. 7 Reserved 0 Reserved. This bit does not manage any functionality. Table 43. HSDC_CFG register (address 0xE706) Bit Location Bit Mnemonic Default value Description 0 HCLK 0 -0: HSCLK is 8MHz -1: HSCLK is 4MHz 1 HSIZE 0 -0: HSDC transmits the 32bit registers in 32bit packages, most significant bit first. |
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