MPC8536EBVTATH datasheet(29/128 Pages) FREESCALE

29 / 128 page

Input Clocks

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

2.4

Input Clocks

2.4.1

System Clock Timing

Table 6 provides the system clock (SYSCLK) AC timing specifications for the MPC8536E.

2.4.2

PCI Clock Timing

When the PCI controller is configured for asynchronous operation, the reference clock for the PCI controller is not the SYSCLK

input, but instead the PCI_CLK. Table 7 provides the PCI reference clock AC timing specifications for the MPC8536E.

2.4.3

Real Time Clock Timing

The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then used as an input to the

counters of the PIC and the TimeBase unit of the e500. There is no jitter specification. The minimum pulse width of the RTC

signal should be greater than 2x the period of the CCB clock. That is, minimum clock high time is 2

× t

CCB, and minimum clock

low time is 2

× t

CCB. There is no minimum RTC frequency; RTC may be grounded if not needed.

Table 6. SYSCLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYSCLK frequency

fSYSCLK

—

133

MHz

SYSCLK cycle time

tSYSCLK

7.5

—

SYSCLK rise and fall time

tKH, tKL

0.61.0

2.1ns

SYSCLK duty cycle

tKHK/tSYSCLK

—

SYSCLK jitter

—

+/-150

3, 4

Notes:

1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting

SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum

operating frequencies. See Section 2.23.2, “CCB/SYSCLK PLL Ratio,” and Section 2.23.3, “e500 Core PLL Ratio,” for ratio

settings.

2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.

3. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.

4. For spread spectrum clocking, guidelines are +0% to -1% down spread at a modulation rate between 20 KHz and 60 KHz on

SYSCLK.

Table 7. PCICLK AC Timing Specifications

At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

PCICLK frequency

fPCICLK

—

MHz

—

PCICLK cycle time

tPCICLK

—

PCICLK rise and fall time

tKH, tKL

0.61.0

2.1ns

PCICLK duty cycle

tKHK/tPCICLK

—

Notes:

1. Rise and fall times for PCICLK are measured at 0.6 V and 2.7 V.

MPC8536EBVTATH 数据表(PDF) 29 Page - Freescale Semiconductor, Inc

MPC8536EBVTATH 数据表(HTML) 29 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载