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MPC8536EBVTATH 数据表(PDF) 79 Page - Freescale Semiconductor, Inc |
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MPC8536EBVTATH 数据表(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 128 page ![]() Serial ATA (SATA) MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 79 Figure 45 provides the AC test load for TDO and the boundary-scan outputs. Figure 45. AC Test Load for the JTAG Interface Figure 46 provides the JTAG clock input timing diagram. Figure 46. JTAG Clock Input Timing Diagram Figure 47 provides the TRST timing diagram. Figure 47. TRST Timing Diagram Figure 48 provides the boundary-scan timing diagram. Figure 48. Boundary-Scan Timing Diagram 2.16 Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the MPC8536E. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. Output Z0 = 50 Ω OVDD/2 RL = 50 Ω JTAG tJTKHKL tJTGR External Clock VM VM VM tJTG tJTGF VM = Midpoint Voltage (OVDD/2) TRST VM = Midpoint Voltage (OVDD/2) VM VM tTRST VM VM tJTDVKH tJTDXKH Boundary Data Outputs JTAG External Clock Boundary Data Inputs Output Data Valid tJTKLDX tJTKLDV Input Data Valid VM = Midpoint Voltage (OVDD/2) |
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