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MPC8536EBVTATH 数据表(PDF) 35 Page - Freescale Semiconductor, Inc |
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MPC8536EBVTATH 数据表(HTML) 35 Page - Freescale Semiconductor, Inc |
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35 / 128 page  DDR2 and DDR3 SDRAM MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35 2.6.2.2 DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications Table 19 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface. Table 19. DDR SDRAM Output AC Timing Specifications At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3. Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 3.0 5 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 667 MHz 1.10 — 7 533 MHz 1.48 — 400 MHz 1.95 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 667 MHz 1.10 — 7 533 MHz 1.48 — 400 MHz 1.95 — MCS[n] output setup with respect to MCK tDDKHCS ns 3 667 MHz 1.10 — 7 533 MHz 1.48 — 400 MHz 1.95 — MCS[n] output hold with respect to MCK tDDKHCX ns 3 667 MHz 1.10 — 7 533 MHz 1.48 — 400 MHz 1.95 — MCK to MDQS Skew tDDKHMH ns 4 <= 667 MHz –0.6 0.6 7 MDQ/MECC/MDM output setup with respect to MDQS tDDKHDS, tDDKLDS ps 5 667 MHz 450 — 7 533 MHz 538 — 400 MHz 700 — MDQ/MECC/MDM output hold with respect to MDQS tDDKHDX, tDDKLDX ps 5 667 MHz 450 — 7 533 MHz 538 — 400 MHz 700 — MDQS preamble start tDDKHMP ns 6 |
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