MPC8536EBVTATH datasheet(63/128 Pages) FREESCALE

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USB

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Figure 35 shows the MII management AC timing diagram.

Figure 35. MII Management Interface Timing Diagram

2.11

USB

This section provides the AC and DC electrical specifications for the USB interface of the MPC8536E.

EC_MDIO to EC_MDC hold time

tMDDXKH

0—

—

EC_MDC rise time

tMDCR

—

EC_MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise

and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual

EC_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of

MPC8536E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform

Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if

MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC = 533/(2*4*8) = 533/64 = 8.3 MHz.

That is, for a system running at a particular platform frequency (fCCB), the EC_MDC output clock frequency can be

programmed between maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. See the MPC8536E reference manual’s

MIIMCFG register section for more detail.

3. This parameter is dependent on the platform clock frequency. The delay is equal to 16 platform clock periods +/-3ns. For

example, with a platform clock of 333MHz, the min/max delay is 48ns +/-3ns. Similarly, if the platform clock is 400MHz, the

min/max delay is 40ns +/-3ns).

5. tCLKplb_clk is the platform (CCB) clock

6. EC_MDC to EC_MDIO Data valid tMDKHDV is a function of clock period and max delay time tMDKHDX. (Min Setup = Cycle

time - Max Hold)

Table 45. MII Management AC Timing Specifications (continued)

At recommended operating conditions with OVDD is 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

EC_MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

EC_MDIO

(Input)

(Output)

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