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(0xB9) are set to Logic 1 whenever the THERM input is

asserted low. The THERM state bits in Host Thermal Status

taken place on the THERM pin.

Figure 83. THERM Behavior

1005C

905C

805C

705C

605C

505C

405C

TEMPERATURE

HIGH TEMP LIMIT

RESET BY MASTER

THERM

ALERT

THERM LIMIT

HYSTERESIS

THERM Timer

The ADT7462 can also measure assertion times on the

THERM inputs as a percentage of a timer window. The timer

window for the THERM1 input is programmed using Bits

[4:2] of the THERM configuration register (0x0D). The

timer window for the THERM2 input is programmed using

Bits [7:5] of the THERM configuration register (0x0D).

Values from 0.25 sec to 8 sec are programmable (see

Table 27).

Table 27. THERM Timer Window

Code

THERM Timer Window

000

0.25 sec

001

0.5 sec

010

1 sec

011

2 sec

100

4 sec

101

8 sec

110

8 sec

111

8 sec

The assertion time as a percentage of the timer window is

stored in the THERM % on−time registers. This is a

cumulative sum of the percentage of time during the

THERM timer window that THERM is asserted. The %

on−time and associated timer limit registers are listed in

Table 28.

Table 28. THERM On−Time and Timer Limit Register

Channel

% On−Time Register

% Timer Limit Register

THERM1

0xAE

0x80

THERM2

0xAF

0x81

When

the

measured

percentage

exceeds

the

corresponding percentage limit, the T1% bit in Host

Thermal Status Register 2 (0xB9) is asserted, and an ALERT

is generated (that is, if the mask bit is not set). If the limit is

set to 0x00, an ALERT is generated on the first assertion. If

the limit is set to 0xFF, an ALERT is never generated

because 0xFF corresponds to the THERM input being

asserted all the time.

When THERM is configured as an input only, setting Bits

[4:1] of the THERM zone in the THERM1 configuration

(0x0F) allows Pin 28/Pin 29 to operate as an I/O.

THERM Timer Limit Register

The THERM timer limit is programmed to Register 0x80

and Register 0x81. If THERM is asserted for longer than the

programmed percentage limit, then an ALERT is generated.

The limit is programmed as a percentage of the chosen

THERM timer window.

EXAMPLE: The THERM timer window is eight seconds,

and an ALERT should be generated if THERM is asserted

for more than one second.

%Limit + 18 100 + 12.5%

The THERM timer limit register is an 8−bit register.

00 + 0%; 0

FF + 100%

Therefore, 1 LSB = 0.39%

12.5%

0.39% +

32 decimal + 0

20 + 00100000

When the time window has elapsed, if the THERM limit

has been exceeded, then an ALERT is generated.

General−Purpose I/O Pins

The ADT7462 has eight open−drain GPIO pins. GPIO1 to

GPIO4 can be configured to enable event driven outputs

(EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO

functionality is enabled. Two other GPIOs (GPIO7 and

GPIO8) are standard GPIO pins that are dedicated to

general−purpose logic input/output.

Each GPIO pin has five data bits associated with it: three

bits in a GPIO configuration register (0x09 and 0x0A), one

in the GPIO status register (0xBF), and one in the GPIO

mask register (0x36).

Setting a direction bit to 1 in a GPIO configuration register

makes the corresponding GPIO pin an output.

Clearing the direction bit to 0 makes the corresponding

GPIO pin an input.

Setting a polarity bit to 1 in a GPIO configuration register

makes the corresponding GPIO pin active high.

Clearing the polarity bit to 0 makes the corresponding

GPIO pin active low.

When a GPIO pin is configured as an input, the

corresponding bit in the GPIO status register is read−only,

and it is set when the input is asserted (“asserted” can be high

or low, depending on the setting of the polarity bit).

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