ADT7462ACPZ-R7 datasheet(52/81 Pages) ONSEMI

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ADT7462

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Bit 4 (VRD2) of Configuration Register 2 (0x02). There is

also an associated mask bit in Register 0x31 to mask the

assertion of these inputs from the ALERT output.

SCSI_TERM Inputs

Pin 16 and Pin 20 can be configured as SCSI_TERM

inputs. An assertion on the SCSI_TERM is recorded in Bit 4

and Bit 5 of Host Digital Status Register (0xBE) or BMC

Digital Status Register (0xC6). There is also an associated

mask bit in Register 0x35 to mask the assertion of these

inputs from the ALERT output.

Reset I/O

The ADT7462 includes an active low reset pin (Pin 14).

The RESET pin can be both a reset input and output. RESET

monitors the VCC input to the ADT7462. At powerup,

RESET is asserted (pulled low) until 180 ms after the power

supply has risen above the supply threshold. A power−on

reset initializes all registers to the default values.

Figure 85. Operation of RESET Output on Powerup

1.0 V

180 ms

VCC

RESET

The RESET pin can also function as a reset input. Pulling

this pin low externally resets the ADT7462. The user should

wait at least 180 ms after powerup before doing a hardware

reset. The reset pulse width should be greater than 0.8 ms to

ensure that a reset is registered.

A hardware reset differs from a power−on reset in that not

all of the registers are reinitialized to the default values. For

example, limit registers are not all restored to the default

values. This can be useful if the user needs to reset the part

but does not want to completely reprogram the device. The

Locked registers are not restored to default values by a

hardware reset.

Note that if two ADT7462 devices are used in one system,

the RESET pins should not be connected together between

devices. Doing so causes one device to reset the other on a

power−on reset.

Software Reset

The ADT7462 can be reset in software by setting Bit 7 of

Configuration Register 0 (0x00). The code 0x6D must be

written to Register 0x7B before setting the software reset bit.

This register is cleared to the power−on default after the

software reset.

Note that not all registers are restored to their default

values on a reset. The same registers are reset by a hardware

and software reset. The Register Map section provides a

complete reference of registers that are reset.

Chassis Intrusion Input

The chassis intrusion (CI) input is an active high input

intended for detection and signaling of unauthorized

tampering with the system. When this input goes high, the

event is latched in Bit 7 of Host Digital Status Register

(0xBE), and an interrupt is generated. The bit remains set

until cleared by writing a 1 to CI reset (CI_R), Bit 5 of

Configuration Register 3 (0x03). The CI reset bit is cleared

by writing a 0 to it.

The CI circuit is powered from the VBATT voltage

channel. Pin 26 must be configured to monitor VBATT and

a battery must be connected to monitor CI events. CI

monitoring is disabled if the measured VBATT value (0x93)

is less than the lower voltage limit (0x75) of Pin 26.

The CI input detects chassis intrusion events even when

the ADT7462 is powered off (provided battery voltage is

applied to VBATT) but does not immediately generate an

interrupt. When a chassis intrusion event is detected and

latched, an interrupt is generated when the system is

powered on.

The actual detection of chassis intrusion is performed by

an external circuit that detects, for example, when the cover

has been removed. A wide variety of techniques can be used

for chassis detection. For example,

• A microswitch that opens or closes when the cover is

removed

• A reed switch operated by a magnet affixed to the cover

• A hall−effect switch operated by a magnet affixed to

the cover

• A photo−transistor that detects light when the cover is

removed

Powerup Sequence

The powerup sequence of the ADT7462 is as follows:

1. The temperature of the thermal diode connected to

Pin 17 and Pin 18 (only dedicated thermal diode

channel) is monitored immediately on powerup of

the ADT7462. Ideally, the hottest zone should be

connected to this channel so protection is provided

immediately on powerup.

2. VCCP1 is also monitored immediately on powerup.

VCCP1 is typically connected to a main power rail.

Switching on the VCCP1 rail gates the fan’s quiet

startup counter.

3. VBATT is monitored immediately on powerup

before the setup complete bit (Register 0x01,

Bit 5) is set. The chassis intrusion circuit (CI) is

powered from VBATT. If the measured VBATT

reading is lower than the lower limit (default =

0x80), the CI circuit is turned off.

4. PWM1, PWM2, and PWM4 are not on dedicated

pins. Because these pins are shared with inputs,

they are allowed to float high on powerup. This

means that if a fan is connected to these pins, it

spins at full speed on powerup.

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