ADT7462ACPZ-R7 datasheet(53/81 Pages) ONSEMI

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ADT7462

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5. PWM3 is switched off by default (because this is a

dedicated pin). If no SMBus communication takes

place within 4.6 seconds of the VCCP rail

switching on, this PWM drive is driven to full

speed. If SMBus communication does take place,

this pin behaves as programmed.

6. No temperature or voltage (other than VCCP1,

Diode 2, and VBATT) is monitored until the setup

complete bit (Bit 5) is set in Configuration

the ADT7462 as required before monitoring of all

channels is enabled, thereby not generating false

ALERTs. The setup complete bit should not be set

until the device is fully configured for the desired

monitoring functions.

The following steps describe how to set up the ADT7462:

1. Powerup the device.

2. Choose the best−suited easy configuration option

for the application, changing pin functions as

required.

3. Program all appropriate limits for monitored

inputs. Program device parameters, fan control

parameters, mask bits, and anything else required

for the application.

4. Set the setup complete bit. Do not set this bit until

the device is fully set up.

XOR Tree Test

The ADT7462 includes an XOR tree test mode. This

mode is useful for in−circuit test equipment at board−level

testing. By applying stimulus to the pins included in the

XOR test, it is possible to detect opens or shorts on the

system board. Figure 86 shows the signals exercised in the

XOR tree test. The XOR tree test is invoked by setting Bit 6

(XOR) of Configuration Register 3 (0x03).

Note that the digital inputs must be selected on

multifunctional pins for the XOR tree test mode. Pin 13 is the

open−drain output of the XOR tree test.

Figure 86. XOR Tree Test

PIN 1

PIN 26

PIN 27

PIN 28

PIN 29

PIN 31

PIN 32

PIN 13

PIN 25

PIN 2

PIN 3

PIN 4

PIN 7

PIN 8

PIN 16

PIN 20

PIN 21

PIN 22

ADT7462ACPZ-R7 数据表(PDF) 53 Page - ON Semiconductor

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