PIC16F720-ESLASHML datasheet(39/244 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41430A-page 39

PIC16F/LF720/721

4.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to

operate without the system clock. The interrupt source

must have the appropriate Interrupt Enable bit(s) set

prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEP instruction. The instruction directly after the

SLEEP

instruction will always be executed before

branching to the ISR. Refer to the Section 19.0

“Power-Down Mode (Sleep)” for more details.

4.4

INT Pin

The

external

interrupt,

INT

pin,

causes

asynchronous, edge-triggered interrupt. The INTEDG bit

of the OPTION register determines on which edge the

interrupt will occur. When the INTEDG bit is set, the

rising edge will cause the interrupt. When the INTEDG

bit is clear, the falling edge will cause the interrupt. The

INTF bit of the INTCON register will be set when a valid

edge appears on the INT pin. If the GIE and INTE bits

are also set, the processor will redirect program

execution to the interrupt vector. This interrupt is

disabled by clearing the INTE bit of the INTCON register.

4.5

Context Saving

When an interrupt occurs, only the return PC value is

saved to the stack. If the ISR modifies or uses an

instruction that modifies key registers, their values

must be saved at the beginning of the ISR and restored

when the ISR completes. This prevents instructions

following the ISR from using invalid data. Examples of

key registers include the W, STATUS, FSR and

PCLATH registers.

The code shown in Example 4-1 can be used to do the

following.

• Save the W register

• Save the STATUS register

• Save the PCLATH register

• Execute the ISR program

• Restore the PCLATH register

• Restore the STATUS register

• Restore the W register

Since most instructions modify the W register, it must

be saved immediately upon entering the ISR. The

SWAPF

instruction is used when saving and restoring

the W and STATUS registers because it will not affect

any bits in the STATUS register. It is useful to place

W_TEMP

in shared memory because the ISR cannot

predict which bank will be selected when the interrupt

occurs.

The processor will branch to the interrupt vector by

loading the PC with 0004h. The PCLATH register will

remain unchanged. This requires the ISR to ensure

that the PCLATH register is set properly before using

an instruction that causes PCLATH to be loaded into

the PC. See Section 2.3 “PCL and PCLATH” for

details on PC operation.

EXAMPLE 4-1:

SAVING W, STATUS AND PCLATH REGISTERS IN RAM

Note:

The microcontroller does not normally

require saving the PCLATH register.

However, if computed GOTOs are used,

the PCLATH register must be saved at the

beginning of the ISR and restored when

the ISR is complete to ensure correct

program flow.

MOVWF W_TEMP

;Copy W to W_TEMP register

SWAPF STATUS,W

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

BANKSELSTATUS_TEMP ;Select regardless of current bank

MOVWF STATUS_TEMP

;Copy status to bank zero STATUS_TEMP register

MOVF

PCLATH,W

;Copy PCLATH to W register

MOVWF

PCLATH_TEMP

;Copy W register to PCLATH_TEMP

:(ISR)

;Insert user code here

BANKSELSTATUS_TEMP ;Select regardless of current bank

MOVF

PCLATH_TEMP,W;

MOVWF

PCLATH

;Restore PCLATH

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS

;Move W into STATUS register

SWAPF W_TEMP,F

;Swap W_TEMP

SWAPF W_TEMP,W

;Swap W_TEMP into W

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