PIC16F720-ESLASHML datasheet(95/244 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS41430A-page 95

PIC16F/LF720/721

13.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

• Synchronous or asynchronous operation

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Time base for the Capture/Compare function

• Special Event Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle Mode

• Gate Single-pulse Mode

• Gate Value Status

• Gate Event Interrupt

Figure 13-1 is a block diagram of the Timer1 module.

FIGURE 13-1:

TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1SYNC

T1CKPS<1:0>

Prescaler

1, 2, 4, 8

Synchronized

clock input

Set flag bit

TMR1IF on

Overflow

TMR1(2)

TMR1ON

Note 1: ST buffer is high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

T1G

FOSC/4

Internal

Clock

T1CKI

TMR1CS<1:0>

(1)

Synchronize(3)

det

Sleep input

TMR1GE

From Timer0

From Timer2

T1GPOL

T1GVAL

Single Pulse

Acq. Control

T1GSPM

T1GGO/DONE

T1GSS<1:0>

FOSC

Internal

Clock

Reserved

From WDT

Overflow

Match PR2

Overflow

T1GCON

Data Bus

det

Interrupt

TMR1GIF

Set

T1CLK

FOSC/2

Internal

Clock

T1G_IN

TMR1ON

T1GTM

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