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PIC16F720-E/ML 数据表(PDF) 41 Page - Microchip Technology

部件名 PIC16F720-E/ML
功能描述  20-Pin Flash Microcontrollers with nanoWatt XLP Technology
PDF  244 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

PIC16F720-E/ML 数据表(HTML) 41 Page - Microchip Technology

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 2010 Microchip Technology Inc.
DS41430A-page 41
PIC16F/LF720/721
4.5.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 4-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 4-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit
1
= Enable the Timer1 gate acquisition complete interrupt
0
= Disable the Timer1 gate acquisition complete interrupt
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit
1
= Enables the ADC interrupt
0
= Disables the ADC interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1
= Enables the USART receive interrupt
0
= Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1
= Enables the USART transmit interrupt
0
= Disables the USART transmit interrupt
bit 3
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1
= Enables the SSP interrupt
0
= Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1
= Enables the CCP1 interrupt
0
= Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1
= Enables the Timer2 to PR2 match interrupt
0
= Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1
= Enables the Timer1 overflow interrupt
0
= Disables the Timer1 overflow interrupt



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