L9803 datasheet(53/126 Pages) STMICROELECTRONICS

53 / 126 page

L9803

On-Chip Peripherals

53/126

= Signal or pulse period (in seconds)

fEXT = External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 28

on page 53).

Note:

After a write instruction to the OCiHR register, the output compare function is inhibited until

the OCiLR register is also written.

The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output

Compare interrupt is inhibited.

The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce

a timer interrupt if the ICIE bit is set and the I bit is cleared.

In PWM mode the ICAP1 pin can not be used to perform input capture because it is

disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can

be set and IC2R can be loaded) but the user must take care that the counter is reset after

each period and ICF1 can also generate an interrupt if ICIE is set.

When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the

PWM mode is the only active one.

Figure 28.

Pulse Width Modulation Mode Timing

5.2.4

Each Timer is associated with three control and status registers, and with six pairs of data

registers (16-bit values) relating to the two input captures, the two output compares, the

counter and the alternate counter.

CONTROL REGISTER 1 (CR1)

Timer1 Register Address: 0032h

Timer2 Register Address: 0042h

Read/Write

Reset Value: 0000 0000(00h)

COUNTER

34E2

FFFC FFFD FFFE

2ED0 2ED1 2ED2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

Note: OCR1=2ED0h, OCR2=34E2, OLVL1=0, OLVL2= 1

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

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