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L9803 数据表(PDF) 74 Page - STMicroelectronics |
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L9803 数据表(HTML) 74 Page - STMicroelectronics |
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74 / 126 page  On-Chip Peripherals L9803 74/126 5.6 Controller Area Network (CAN) 5.6.1 Introduction This peripheral is designed to support serial data exchanges using a multi-master contention based priority scheme as described in CAN specification Rev. 2.0 part A. It can also be connected to a 2.0 B network without problems, since extended frames are checked for correctness and acknowledged accordingly although such frames cannot be transmitted nor received. The same applies to overload frames which are recognized but never initiated. Figure 37. CAN Block Diagram TX/RX Buffer 1 10 Bytes TX/RX Buffer 2 10 Bytes TX/RX Buffer 3 10 Bytes ID Filter 0 4 Bytes ID Filter 1 4 Bytes ST7 Interface PSR ICR ISR BRPR CSR TECR RECR CAN 2.0B passive Core SHREG BCDL CRC BTL RX TX EML ST7 Internal Bus BTR |
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