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L9803 数据表(PDF) 43 Page - STMicroelectronics |
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L9803 数据表(HTML) 43 Page - STMicroelectronics |
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43 / 126 page  L9803 On-Chip Peripherals 43/126 The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 9: Clock Control Bits. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f CPU/2, fCPU/4, fCPU/8 or an external frequency. Figure 19. Timer Block Diagram MCU-PERIPHERAL INTERFACE COUNTER ALTERNATE REGISTER OUTPUT COMPARE REGISTER OUTPUT COMPARE EDGE DETECT OVERFLOW DETECT CIRCUIT 1/2 1/4 1/8 8-bit buffer ST7 INTERNAL BUS LATCH1 OCMP1 ICAP1 EXCLK CPU CLOCK TIMER INTERRUPT ICF2 ICF1 0 0 0 OCF2 OCF1 TOF PWM OC1E EXEDG IEDG2 CC0 CC1 OC2E OPM FOLV2 ICIE OLVL1 IEDG1 OLVL2 FOLV1 OCIE TOIE ICAP2 LATCH2 OCMP2 8 8 8 low 16 8 high 16 16 16 16 CR1 CR2 SR 6 16 8 8 8 8 8 8 EXEDG TIMER INTERNAL BUS CIRCUIT1 EDGE DETECT CIRCUIT2 CIRCUIT 1 OUTPUT COMPARE REGISTER 2 INPUT CAPTURE REGISTER 1 INPUT CAPTURE REGISTER 2 CC1 CC0 16 BIT FREE RUNNING COUNTER |
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