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L9803 数据表(PDF) 45 Page - STMicroelectronics |
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L9803 数据表(HTML) 45 Page - STMicroelectronics |
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45 / 126 page  L9803 On-Chip Peripherals 45/126 Figure 20. Counter Timing Diagram, internal clock divided by 2 Figure 21. Counter Timing Diagram, internal clock divided by 4 Figure 22. Counter Timing Diagram, internal clock divided by 8 Input Capture In this section, the index, i, may be 1 or 2 The two input capture 16-bit registers (ICR1 and ICR2) are used to latch the value of the free running counter after a transition detected by the ICAPi pin (see figure 5) . ICRi register is a read-only register. MS Byte LS Byte ICRi ICHRi ICLRi CPU CLOCK FFFD FFFE FFFF 0000 0001 0002 0003 INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF FFFC FFFD 0000 0001 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER OVERFLOW FLAG TOF FFFC FFFD 0000 |
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