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L9803 数据表(PDF) 37 Page - STMicroelectronics |
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L9803 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 126 page  L9803 On-Chip Peripherals 37/126 be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 17. Interrupt I/O Port State Transitions I/O Port Implementation The I/O port register configurations are resumed as following. Port PA(7:0), Port PB(2:0) RESET status: DR=0, DDR=0 and OR=0 (Input mode, no interrupt). These ports offer interrupt capabilities. DDR OR MODE 00 input no interrupt (pull-up enabled) 01 input interrupt (pull-up enabled) 1 0 Open-Drain output 1 1 Push-Pull output 01 floating/pull-up interrupt INPUT 00 floating (reset state) INPUT 10 open-drain OUTPUT 11 push-pull OUTPUT XX = DDR, OR |
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