L9803 datasheet(103/126 Pages) STMICROELECTRONICS

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L9803

On-Chip Peripherals

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5.9.3

EEPROM CONTROL REGISTER (EECR)

Address: 002Ch - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = E2ITE: Interrupt enable.

This bit is set and cleared by software.

0: Interrupt disabled

1: Interrupt enabled

When the programming cycle is finished (E2PGM toggle from 1 to 0), an interrupt is

generated only if E2ITE is high. The interrupt is automatically cleared when the micro-

controller enters the EEPROM interrupt routine.

Bit 1 = E2LAT: Read/Write mode.

This bit is set by software. It is cleared by hardware at the end of the programming cycle. It

can be cleared by software only if E2PGM=0.

0: Read mode

1: Write mode

When E2LAT=1, if the E2PGM bit is low and the micro-controller is in write mode, the 8 bit

data bus is stored in one of the four groups of 8 bit data latches, selected by the address.

This happens every time the device executes an EEPROM Write instruction. If E2PGM

remains low, the content of the 8 bit data latches is not transferred into the matrix, because

the High Voltage charge-pump does not start. The 8 data latches are selected by the lower

part of the address (A<1:0> bits). If 4 consecutive write instructions are executed, by

sweeping from A<1:0>=0h to A<1:0>=3h, with the same higher part of the address, all the 4

groups of data latches will be written, and they will be ready to write a whole row of the

EEPROM matrix, as soon as E2PGM goes high and the charge-pump starts. If only one

write instruction is executed before E2PGM goes high, only one group of data latches will be

selected and only one byte of the matrix will be written. At the end of the programming cycle,

E2LAT bit is automatically cleared, and the data latches are cleared.

Bit 0 = E2PGM: Programming Control.

This bit is set by software to begin the programming cycle. At the end of the programming

cycle, this bit is cleared by hardware and an interrupt is generated if the E2ITE bit is set.

0: Programming finished or not started

1: Programming cycle is in progress

Note:

if the E2PGM bit is cleared during the programming cycle, the memory data is not

guaranteed.

Note:

Care should be taken during the programming cycle. Writing to the same memory location

will over-program the memory (logical AND between the two write access data result)

because the data latches are only cleared at the end of the programming cycle and by the

E2ITE

E2LAT

E2PGM

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