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MPC8572ECLPXAVND 数据表(PDF) 20 Page - Freescale Semiconductor, Inc |
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MPC8572ECLPXAVND 数据表(HTML) 20 Page - Freescale Semiconductor, Inc |
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20 / 140 page ![]() MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 20 Freescale Semiconductor DDR2 and DDR3 SDRAM Controller Table 12 provides the DDR SDRAM Controller interface capacitance for DDR2 and DDR3. Table 13 provides the current draw characteristics for MVREFn. 6.2 DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR SDRAM Controller interface. The DDR controller supports both DDR2 and DDR3 memories. Note that although the minimum data rate for most off-the-shelf DDR3 DIMMs available is 800 MHz, JEDEC specification does allow the DDR3 to run at the data rate as low as 606 MHz. Unless otherwise specified, the AC timing specifications described in this section for DDR3 is applicable for data rate between 606 MHz and 800 MHz, as long as the DC and Output leakage current IOZ –50 50 μA3 Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREFn may not exceed ±1% of the DC value. 3. Output leakage is measured with all outputs disabled, 0 V ≤ V OUT ≤ GVDD. Table 12. DDR2 and DDR3 SDRAM Interface Capacitance for GVDD(typ)=1.8 V and 1.5 V Parameter/Condition Symbol Min Typical Max Unit Input/output capacitance: DQ, DQS, DQS CIO 6 8 pF 1, 2 Delta input/output capacitance: DQ, DQS, DQS CDIO — 0.5 pF 1, 2 Note: 1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V. 2. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.175 V. Table 13. Current Draw Characteristics for MVREF n Parameter / Condition Symbol Min Max Unit Note Current draw for MVREFn DDR2 SDRAM IMVREFn — 1500 μA1 DDR3 SDRAM 1250 1. The voltage regulator for MVREFn must be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3 respectively. Table 11. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V (continued) Parameter/Condition Symbol Min Typical Max Unit |
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