MPC8572ECLPXAVND datasheet(71/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

14.2

GPIO AC Electrical Specifications

Table 58 provides the GPIO input and output AC timing specifications.

Figure 42 provides the AC test load for the GPIO.

Figure 42. GPIO AC Test Load

15 High-Speed Serial Interfaces (HSSI)

The MPC8572E features two Serializer/Deserializer (SerDes) interfaces to be used for high-speed serial

interconnect applications. The SerDes1 interface can be used for PCI Express and/or Serial RapidIO data

transfers. The SerDes2 is dedicated for SGMII application.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes Reference Clocks. The SerDes data lane’s transmitter and receiver reference

circuits are also shown.

15.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 43 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for

description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a

receiver input (SDn_RX and SDn_RX). Each signal swings between A Volts and B Volts where A > B.

Using this waveform, the definitions are as follows. To simplify illustration, the following definitions

assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling

environment.

1. Single-Ended Swing

The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and

SDn_RX each have a peak-to-peak swing of A - B Volts. This is also referred as each signal wire’s

Single-Ended Swing.

Table 58. GPIO Input AC Timing Specifications1

Parameter

Symbol

Typ

Unit

Notes

GPIO inputs—minimum pulse width

tPIWID

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYSCLK. Timings

are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.

Output

Z0 = 50 Ω

BVDD/2

RL = 50 Ω

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