MPC8572ECLPXAVND datasheet(52/140 Pages) FREESCALE

52 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet Management Interface Electrical Characteristics

Figure 28 shows the MII management AC timing diagram.

Figure 28. MII Management Interface Timing Diagram

ECn_MDIO to ECn_MDC hold time

tMDDXKH

0—

—

ECn_MDC rise time

tMDCR

—

ECn_MDC fall time

tMDHF

—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)

(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX

symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are

invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input

signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For

rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual

ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of

MPC8572E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform

Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if

MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC = 533/(2*4*8) = 533/64 = 8.3 MHz.

That is, for a system running at a particular platform frequency (fCCB), the ECn_MDC output clock frequency can be

programmed between maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. Refer to MPC8572E reference manual’s

MIIMCFG register section for more detail.

3. The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for MPC8572E

(600 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform

frequency for MPC8572E (400 MHz) divided by 448, following the formula described in Note 2 above. The typical

ECn_MDC output clock frequency of 2.5 MHz is shown for reference purpose per IEEE 802.3 specification.

4. Guaranteed by design.

5. tplb_clk is the platform (CCB) clock.

Table 44. MII Management AC Timing Specifications (continued)

At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

ECn_MDC

tMDDXKH

tMDC

tMDCH

tMDCR

tMDCF

tMDDVKH

tMDKHDX

ECn_MDIO

(Input)

(Output)

MPC8572ECLPXAVND 数据表(PDF) 52 Page - Freescale Semiconductor, Inc

MPC8572ECLPXAVND 数据表(HTML) 52 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载