MPC8572ECLPXAVND datasheet(18/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

RESET Initialization

For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency

should be no more than 127 MHz.

For 8-bit Encoded FIFO mode:

FIFO TX/RX clock frequency <= platform clock (CCB) frequency/3.2

For example, if the platform (CCB) frequency is 533 MHz, the FIFO TX/RX clock frequency

should be no more than 167 MHz.

4.6

Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes and eTSEC,

see the respective sections of this document.

RESET Initialization

Table 8 describes the AC electrical specifications for the RESET initialization timing.

Table 9 provides the PLL lock times.

Table 8. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs2

Minimum assertion time for SRESET

—

SYSCLKs

PLL config input setup time with stable SYSCLK before HRESET

negation

100

—

μs—

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs

with respect to negation of HRESET

—

SYSCLKs

Notes:

1. SYSCLK is the primary clock input for the MPC8572E.

2. Reset assertion timing requirements for DDR3 DRAMs may differ.

Table 9. PLL Lock Times

Parameter/Condition

Symbol

Min

Typical

Max

PLL lock times

—

100

μs—

Local bus PLL

—

μs—

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