 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
MPC8572ECLPXAVND 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8572ECLPXAVND 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
|
|
22 / 140 page  MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4 22 Freescale Semiconductor DDR2 and DDR3 SDRAM Controller Figure 3 shows the DDR2 and DDR3 SDRAM interface input timing diagram. Figure 3. DDR2 and DDR3 SDRAM Interface Input Timing Diagram 6.2.2 DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications Table 17 contains the output AC timing targets for the DDR2 and DDR3 SDRAM interface. Table 17. DDR2 and DDR3 SDRAM Interface Output AC Timing Specifications At recommended operating conditions with GVDD of 1.8 V ± 5% for DDR2 or 1.5 V ± 5% for DDR3. Parameter Symbol 1 Min Max Unit Notes MCK[n] cycle time tMCK 2.5 5 ns 2 ADDR/CMD output setup with respect to MCK tDDKHAS ns 3 800 MHz 0.917 — 667 MHz 1.10 — 533 MHz 1.48 — 400 MHz 1.95 — ADDR/CMD output hold with respect to MCK tDDKHAX ns 3 800 MHz 0.917 — 667 MHz 1.10 — 533 MHz 1.48 — 400 MHz 1.95 — MCS[n] output setup with respect to MCK tDDKHCS ns 3 800 MHz 0.917 — 667 MHz 1.10 — 533 MHz 1.48 — MCK[n] MCK[n] tMCK MDQ[x] MDQS[n] tDISKEW D1 D0 tDISKEW tDISKEW |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
