MPC8572ECLPXAVND datasheet(99/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Serial RapidIO

by Clause 47. Additionally, the CJPAT test pattern defined in Annex 48A of IEEE 802.3ae-2002 is

specified as the test pattern for use in eye pattern and jitter measurements. Annex 48B of IEEE

802.3ae-2002 is recommended as a reference for additional information on jitter test methods.

17.8.1

Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point

at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the

Continuous Jitter Test Pattern (CJPAT) defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial

link shall be active in both the transmit and receive directions, and opposite ends of the links shall use

asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane

implementations shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. The

amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12.

The eye pattern shall be measured with AC coupling and the compliance template centered at 0 Volts

differential. The left and right edges of the template shall be aligned with the mean zero crossing points of

the measured data eye. The load for this test shall be 100

Ω resistive +/– 5% differential to 2.5 GHz.

17.8.2

Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud

Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter

Test Pattern (CJPAT) pattern defined in Annex 48A of IEEE 802.3ae. All lanes of the LP-Serial link shall

be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous

clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations

shall use the CJPAT sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured

with AC coupling and at 0 Volts differential. Jitter measurement for the transmitter (or for calibration of a

jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that

described in Annex 48B of IEEE 802.3ae.

17.8.3

Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100

Ω resistive +/– 5%

differential to 2.5 GHz.

17.8.4

Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first

producing the sum of deterministic and random jitter defined in Section 8.6 and then adjusting the signal

amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template

shown in Figure 8-4 and Table 8-11. Note that for this to occur, the test signal must have vertical waveform

symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero

crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using

a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The

required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced

by the receiver being tested.

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