MPC8572ECLPXAVND datasheet(58/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Local Bus Controller (eLBC)

Figure 30 through Figure 35 show the local bus signals.

Figure 30. Local Bus Signals, Non-Special Signals Only (PLL Enabled)

Table 51 describes the general timing parameters of the local bus interface at BVDD = 3.3 V DC with PLL

disabled.

Table 51. Local Bus General Timing Parameters—PLL Bypassed

At recommended operating conditions with BVDD of 3.3 V ± 5%

Parameter

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

—

Internal launch/capture clock to LCLK delay

tLBKHKT

2.3

4.0

—

Input setup to local bus clock (except

LGTA/LUPWAIT)

tLBIVKH1

5.8

—

4, 5

LGTA/LUPWAIT input setup to local bus clock

tLBIVKL2

5.7

—

4, 5

Input hold from local bus clock (except

LGTA/LUPWAIT)

tLBIXKH1

-1.3

—

4, 5

LGTA/LUPWAIT input hold from local bus clock

tLBIXKL2

-1.3

—

4, 5

Output Signals:

LA[27:31]/LCS[0:7]/LWE[0:3]/

LFWE/LBCTL/LFCLE/

LFALE/LOE/LFRE/LFWP

tLBKHOV1

tLBKHOV2

tLBKHOV3

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3]

Output (Address) Signal:

LAD[0:31]

LALE

tLBIXKH1

tLBIVKH1

tLBIVKH2

tLBIXKH2

tLBKHOX1

tLBKHOZ1

tLBKHOX2

tLBKHOZ2

Input Signal:

LGTA/LFRB

tLBOTOT

tLBKHOZ2

tLBKHOX2

tLBKHOV4

LUPWAIT

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