MPC8572ECLPXAVND datasheet(38/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 16 shows the TBI receive AC timing diagram.

Figure 16. TBI Receive AC Timing Diagram

8.2.5

TBI Single-Clock Mode AC Specifications

When the eTSEC is configured for TBI modes, all clocks are supplied from external sources to the relevant

eTSEC interface. In single-clock TBI mode, when a 125-MHz TBI receive clock is supplied on TSECn

pin (no receive clock is used in this mode, whereas for the dual-clock mode this is the PMA1 receive

clock). The 125-MHz transmit clock is applied in all TBI modes.

A summary of the single-clock TBI mode AC specifications for receive appears in Table 32.

Table 32. TBI single-clock Mode Receive AC Timing Specification

At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

RX_CLK clock period

tTRRX

7.5

8.0

8.5

RX_CLK duty cycle

tTRRH/tTRRX

RX_CLK peak-to-peak jitter

tTRRJ

—

250

Rise time RX_CLK (20%–80%)

tTRRR

——

1.0

Fall time RX_CLK (80%–20%)

tTRRF

——

1.0

RCG[9:0] setup time to RX_CLK rising edge

tTRRDVKH

2.0

—

RCG[9:0] hold time to RX_CLK rising edge

tTRRDXKH

1.0

—

TBI Receive Clock 1

RCG[9:0]

tTRX

tTRXH

tTRXR

tTRXF

tTRDVKH

TBI Receive Clock 0

tTRDXKH

tTRDVKH

tTRDXKH

tSKTRX

tTRXH

Valid Data

(TSEC

n_TX_CLK)

(TSEC

n_RX_CLK)

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