MPC8572ECLPXAVND datasheet(89/140 Pages) FREESCALE

89 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

PCI Express

16.5

Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 56 is specified using the passive compliance/test measurement load (see

Figure 57) in place of any real PCI Express RX component.

Note: In general, the minimum Receiver eye diagram measured with the compliance/test measurement

load (see Figure 57) is larger than the minimum Receiver eye diagram measured over a range of systems

at the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver

is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI

Express component to vary in impedance from the compliance/test measurement load. The input Receiver

eye diagram is implementation specific and is not specified. RX component designer should provide

additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in

Figure 56) expected at the input Receiver based on some adequate combination of system simulations and

the Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned

in time using the jitter median to locate the center of the eye diagram.

The eye diagram must be valid for any 250 consecutive UIs.

A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is

created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX

UI.

NOTE

The reference impedance for return loss measurements is 50. to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50. probes—see Figure 57). Note that the series capacitors, CTX, are

optional for the return loss measurement.

Figure 56. Minimum Receiver Eye Timing and Voltage Compliance Specification

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