MPC8572ECLPXAVND datasheet(79/140 Pages) FREESCALE

79 / 140 page

MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

Figure 50. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

Figure 51 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with MPC8572E SerDes reference clock

input’s DC requirement.

Figure 51. Single-Ended Connection (Reference Only)

15.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and

cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and

is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise

n_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8572E

10nF

n_REF_CLK

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

Single-Ended

CLK Driver Chip

MPC8572E

Total 50

Ω. Assume clock driver’s

output impedance is about 16

Ω.

MPC8572ECLPXAVND 数据表(PDF) 79 Page - Freescale Semiconductor, Inc

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