MPC8572ECLPXAVND datasheet(32/140 Pages) FREESCALE

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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4

Freescale Semiconductor

Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

Figure 8. FIFO Receive AC Timing Diagram

8.2.2

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1

GMII Transmit AC Timing Specifications

Table 26 provides the GMII transmit AC timing specifications.

Table 26. GMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/TVDD of 2.5/ 3.3 V ± 5%.

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

GMII data TXD[7:0], TX_ER, TX_EN setup time

tGTKHDV

2.5

——ns

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

tGTKHDX

0.5

—

5.0

GTX_CLK data clock rise time (20%-80%)

tGTXR

——

1.0

GTX_CLK data clock fall time (80%-20%)

tGTXF

——

1.0

Notes:

1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII

transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input

signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect

to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold

time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a

particular functional. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times,

the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Guaranteed by design.

tFIR

tFIRH

tFIRF

tFIRR

RX_CLK

RXD[7:0]

RX_DV

RX_ER

valid data

tFIRDX

tFIRDV

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