FULLFLEX datasheet(49/52 Pages) CYPRESS

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FullFlex

Document Number: 38-06082 Rev. *K

Page 49 of 52

Document History Page

Document Title: FullFlex™ Synchronous SDR Dual Port SRAM

Document Number: 38-06082

REV.

ECN NO. Submission

Date

Orig. of

Change

Description of Change

302411

See ECN

YDT

New data sheet

334036

See ECN

YDT

Corrected typo on page 1

Reproduced PDF file to fix formatting errors

395800

See ECN

SPN

Added statement about no echo clocks for flow through mode

Updated electrical characteristics

Added note 16 and 17 (1.5 V timing)

Added note 33 (timing for x18 devices)

Updated input edge rate (note 34)

Updated table 5 on deterministic access control logic

Added description of busy readback in deterministic access control section

Changed dummy write descriptions

Updated ZQ pins connection details

Updated note 24, B0 to BE0

Added power supply requirements to MRST and VC_SEL

Added note 4 (VIM disable)

Updated supply voltage to ground potential to 4.1 V

Updated parameters on table 15

Updated and added parameters to table 16

Updated x72 pinout to SDR only pinout

Updated 484 PBGA pin diagram

Updated the pin definition of MRST

Updated the pin definition of VC_SEL

Updated READY description to include Wired OR note

Updated master reset to include wired OR note for READY

Updated minimum VOH value for the 1.8 V LVCMOS configuration

Updated electrical characteristics to include IOH and IOL values

Updated electrical characteristics to include READY

Added IIX3

Updated maximum input capacitance

Added Notes 33 and 34Removed Notes 15 and 17

Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1

Removed -100 Speed bin from Table.1 Selection Guide

Changed voltage name from VDDQ to VDDIO

Changed voltage name from VDD to VCORE

Moved the Mailbox Interrupt Timing Diagram to be the final timing diagram

Updated the Package Type for the CYD36S18V18 parts

Updated the Package Type for the CYD18S18V18 parts

Updated the Package Type for the CYD18S36V18 parts

Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256

Included an OE Controlled Write for Flow through Mode Switching Waveform

Included a Read with Echo Clock Switching Waveform

Updated Figure 5 and Figure 6

Updated Electrical Characteristics for READY VOH and READY V

Updated Electrical Characteristics for VOH and VOL for the -167 and -133 speeds

Included a Unit column for Table 5

Removed Switching Characteristic tCA from chart

Included tOHZ in Switching Waveform OE Controlled Write for Pipelined Mode

Included tCKLZ2 in Waveform Read-to-Write-to-Read for Flow through Mode

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FULLFLEX 数据表(PDF) 49 Page - Cypress Semiconductor

FULLFLEX 数据表(HTML) 49 Page - Cypress Semiconductor

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FULLFLEX 数据表(PDF) 49 Page - Cypress Semiconductor

FULLFLEX 数据表(HTML) 49 Page - Cypress Semiconductor

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