FULLFLEX datasheet(51/52 Pages) CYPRESS

51 / 52 page

FullFlex

Document Number: 38-06082 Rev. *K

Page 51 of 52

2505003

See ECN

VKN/

AESA

Modified footnote #1

Removed 250 MHz speed bin

Added 2-Mbit part and it’s related information

Changed ball name ZQ1 to DNU for 18M and lesser density devices

Added 256-Ball (17 x 17 mm) BGA package for 18M

Made PORTSTD[1:0] left and right pins driven only by LVTTL reference level

For 1.8V LVCMOS level, Changed VIH(min) from 1.26V to 0.65 times VDDIO and

Changed VIL(max) from 0.36V to 0.35 times VDDIO

Changed tHD, tHAC specs for 36M from 0.6 ns/0.7 ns to 0.8 ns (See footnote# 32)

Updated Ordering Information table

2898491

07/01/2010

RAME

Modified “Counter Load Operation” section on page 12 and in Table7. on page 13.

Corrected typo in Table 14. by making LowSPD = 0 for tCD1 spec in the description.

Modified figure 16. on page 30.

Removed inactive parts from Ordering Information.

Updated Packaging Information.

Corrected “ Counter Interrupt operation” Section in Page 14 of the datasheet

Updated ordering information with the parts, CYD02S36V18-200BBC and

CYD36S72V18-167BGI.

2995098

07/28/2010

RAME

Updated Ordering Information and added Ordering Code Definitions.

Added Acronyms and Units of Measure.

Minor edits.

3267210

05/26/2011

ADMU

Updated Electrical Characteristics on page 21 (Removed 133 MHz speed bin).

Updated Switching Characteristics on page 26 (Removed 133 MHz speed bin).

Removed information for 4Mb devices.

Updated Ordering Information.

Document History Page (continued)

Document Title: FullFlex™ Synchronous SDR Dual Port SRAM

Document Number: 38-06082

REV.

ECN NO. Submission

Date

Orig. of

Change

Description of Change

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