 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
FULLFLEX 数据表(PDF) 12 Page - Cypress Semiconductor |
|
|
|||||||||||||||||||||||||||||
FULLFLEX 数据表(HTML) 12 Page - Cypress Semiconductor |
|
|
12 / 52 page  FullFlex Document Number: 38-06082 Rev. *K Page 12 of 52 address matches enable to generate the BUSY flag. However, none of the addresses are saved into the busy address register. When a busy readback is performed, the address of the first match that happens at least two clocks cycles after the busy readback is saved into the busy address register. Variable Impedance Matching Each port contains a variable impedance matching circuit to set the impedance of the IO driver to match the impedance of the on-board traces. The impedance is set for all outputs except JTAG and is done by port. To take advantage of the VIM feature, connect a calibrating resistor (RQ) that is five times the value of the intended line impedance from the ZQ[1:0][27] pin to VSS. The output impedance is then adjusted to account for drifts in supply voltage and temperature every 1024 clock cycles. If a port’s clock is suspended, the VIM circuit retains its last setting until the clock is restarted. On restart, it then resumes periodic adjustment. In the case of a significant change in device temperature or supply voltage, recalibration happens every 1024 clock cycles. A master reset initializes the VIM circuitry. Table 5 shows the VIM parameters and Table 6 describes the VIM operation modes. To disable VIM, connect the ZQ pin to VDDIO of the relative supply for the IOs before a Master Reset. Table 3. tCCS Timing for All Operating Modes Port A—Early Arriving Port Port B—Late Arriving Port tCCS C Rise to Opposite C Rise Setup Time for Non Corrupt Data Unit Mode Active Edge Mode Active Edge SDRCSDR C tCYC(min) – 0.5 ns Table 4. Deterministic Access Control Logic Left Port Right Port Left Clock Right Clock BUSYL BUSYR Description Read Read X X H H No collision Write Read > tCCS 0 H H Read OLD data 0> tCCS H H Read NEW data < tCCS 0 H H Read OLD data H L Data not guaranteed 0< tCCS H H Read NEW data H L Data Not guaranteed Read Write > tCCS 0 H H Read NEW data 0> tCCS HH Read OLD data < tCCS 0 H H Read NEW data L H Data Not guaranteed 0< tCCS HH Read OLD data L H Data not guaranteed Write Write 0 > –tCCS & < tCCS L L Array data corrupted 0> tCCS L H Array stores right port data > tCCS 0 H L Array stores left port data Table 5. Variable Impedance Matching Parameters Parameter Min Max Unit Tolerance RQ value 100 275 ±2% Output impedance 20 55 ±15% Reset time – 1024 Cycles – Update time – 1024 Cycles – Table 6. Variable Impedance Matching Operation RQ Connection Output Configuration 100 –275 to VSS Output driver impedance = RQ/5 ± 15% at Vout = VDDIO/2 ZQ to VDDIO VIM disabled. Rout < 20 at Vout = VDDIO/2 Note 27. The pin ZQ[1] is applicable only for 36 Mbit devices. This pin is DNU for 18 Mbit and lower density devices. [+] Feedback |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
