FULLFLEX datasheet(18/52 Pages) CYPRESS

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FullFlex

Document Number: 38-06082 Rev. *K

Page 18 of 52

Master Reset

The FullFlex family of Dual Ports undergoes a complete reset

when MRST is asserted. MRST must be driven by VDDIOL

referenced levels. The MRST is asserted asynchronously to the

clocks and must remain asserted for at least tRS. When asserted

MRST deasserts READY, initializes the internal burst counters,

internal mirror registers, and internal busy addresses to zero. It

also initializes the internal mask register to all 1s. All mailbox

interrupts (INT), busy address outputs (BUSY), and burst

counter interrupts (CNTINT) are deasserted upon master reset.

Additionally, do not release MRST until all power supplies

including VREF are fully ramped and all port clocks and mode

select inputs (LOWSPD, ZQ, CQEN, FTSEL, and PORTSTD)

are valid and stable. This begins calibration of the DLL and VIM

circuits. READY is asserted within 1024 clock cycles. READY is

a wired OR capable output with a strong pull up and weak pull

down. Up to four outputs may be connected together. For faster

pull down of the signal, connect a 250 Ohm resistor to VSS. If

the DLL and VIM circuits are disabled for a port, the port is

operational within five clock cycles. However, the READY is

asserted within 160 clock cycles.

IEEE 1149.1 Serial Boundary Scan (JTAG)

The FullFlex families incorporate an IEEE 1149.1 serial

boundary scan test access port (TAP). The TAP operates using

JEDEC-standard 3.3 V or 2.5 V IO logic levels depending on the

VTTL power supply. It is composed of four input connections and

one output connection required by the test logic defined by the

standard.

Table 9. JTAG IDCODE Register Definitions

Part Number

Configuration

Value

CYD36S72V18

512 K × 72

0C026069h (×2)

CYD36S36V18

1024 K × 36

0C023069h

CYD36S18V18

2048 K × 18

0C024069h

CYD18S72V18

256 K × 72

0C025069h

CYD18S36V18

512 K × 36

0C026069h

CYD18S18V18

1024 K × 18

0C027069h

CYD09S72V18

128 K × 72

0C028069h

CYD09S36V18

256 K × 36

0C029069h

CYD09S18V18

512 K × 18

0C02A069h

CYD02S36V18

64 K × 36

0C030069h

Table 10. Scan Registers Sizes

Bit Size

Instruction

Bypass

Identification

Boundary Scan

n[39]

Table 11. Instruction Identification Codes

Instruction

Code

Description

EXTEST

0000

Captures the input and output ring contents. Places the BSR between the TDI and TDO.

BYPASS

1111

Places the BYR between TDI and TDO.

IDCODE

1011

Loads the IDR with the vendor ID code and places the register between TDI and TDO.

HIGHZ

0111

Places BYR between TDI and TDO. Forces all FullFlex72 and FullFlex36 output drivers to a

High Z state.

CLAMP

0100

Controls boundary to 1 or 0. Places BYR between TDI and TDO.

SAMPLE/PRELOAD

1000

Captures the input and output ring contents. Places BSR between TDI and TDO.

RESERVED

All other

codes

Other combinations are reserved. Do not use other than the mentioned combinations.

Note

39. Details of the boundary scan length is found in the BSDL file for the device.

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