FULLFLEX datasheet(14/52 Pages) CYPRESS

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FullFlex

Document Number: 38-06082 Rev. *K

Page 14 of 52

Table 7. Burst Counter and Mask Register Control Operations

The burst counter and mask register control operation for any port follows. [29, 30]

MRST CNTRST CNT/MSK CNTEN ADS RET

Operation

Description

Master reset

Reset address counter to all 0s, mask

Counter reset

Reset counter and mirror unmasked portion

to all 0s.

Mask reset

Reset mask register to all 1s.

Counter

load

for

burst/external address

load for non-burst

Load burst counter and mirror with external

address value presented on address lines.

Mask load

Load mask register with value presented on

the address lines.

Retransmit

Load counter with value in the mirror register.

Counter increment

Internally increment address counter value.

Counter hold

Constantly hold the address value for

multiple clock cycles.

Counter readback

Read out counter internal value on address

lines.

Mask readback

Read out mask register value on address

lines.

Busy

address

readback

Read out first busy address after last busy

address readback.

Reserved

Notes

29. “X” = Don’t Care, “H” = HIGH, “L” = LOW.

30. Counter operation and mask register operation is independent of chip enables.

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