FullFlex

Document Number: 38-06082 Rev. *K

Page 20 of 52

READY

Output HIGH voltage

LVTTL

2.7[42]

––

V

HSTL(DC)[43]

VDDIO – 0.4[42]

––

V

HSTL (AC)[43]

VDDIO – 0.5[42]

––

V

2.5 V LVCMOS

2.0[42]

––

V

1.8 V LVCMOS

VDDIO – 0.45[42]

––

V

READY

Output HIGH voltage

LVTTL

–

–

0.4[42]

V

HSTL(DC)[43]

––

0.4[42]

V

HSTL (AC)[43]

––

0.5[42]

V

2.5 V LVCMOS

–

–

0.7[42]

V

1.8 V LVCMOS

–

–

0.45[42]

V

Output leakage current

–10

–

10

A

Input leakage current except

TDI, TMS, MRST, PORTSTD

–10

–

10

A

Input leakage current TDI,

TMS, MRST

–300

–

10

A

Input leakage current

PORTSTD

–10

–

300

A

Over the Operating Range

Parameter

Description

Configuration

All Speed Bins

Unit

Min

Typ

Max

Notes

42. These parameters are met with VIM disabled.

43. The DC specifications are measured under steady state conditions. The AC specifications are measured while switching at speed. AC VIH/VIL in HSTL mode are

measured with 1 V/ns input edge rates.

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