FULLFLEX datasheet(10/52 Pages) CYPRESS

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FullFlex

Document Number: 38-06082 Rev. *K

Page 10 of 52

PORTSTD[1:0]L[26] PORTSTD[1:0]R[26] Port clock/Address/Control/Data/Echo clock/I/O standard select input. Assert these pins

LOW/LOW for LVTTL, LOW/HIGH for HSTL, HIGH/LOW for 2.5 V LVCMOS, and HIGH/HIGH

for 1.8 V LVCMOS, respectively. These pins are driven by VTTL referenced levels.

R/WL

R/WR

Read/Write enable input. Assert this pin LOW to write to, or HIGH to read from the dual port

memory array.

READYL

READYR

Port DLL ready output. This signal is asserted LOW when the DLL and variable impedance

matching circuits complete calibration. This is a wired OR capable output.

CNT/MSKL

CNT/MSKR

Port counter/Mask select input. Counter control input.

ADSL

ADSR

Port counter address load strobe input. Counter control input.

CNTENL

CNTENR

Port counter enable input. Counter control input.

CNTRSTL

CNTRSTR

Port counter reset input. Counter control input.

CNTINTL

CNTINTR

Port counter interrupt output. This pin is asserted LOW one cycle before the unmasked portion

of the counter is incremented to all “1s”.

WRPL

WRPR

Port counter wrap input. When the burst counter reaches the maximum count, on the next

counter increment WRP is set LOW to load the unmasked counter bits to 0. It is set HIGH to load

the counter with the value stored in the mirror register.

RETL

RETR

Port counter retransmit input. Assert this pin LOW to reload the initial address for repeated

access to the same segment of memory.

VREFL

VREFR

Port external HSTL IO reference input. This pin is left DNU when HSTL is not used.

VDDIOL

VDDIOR

Port data IO power supply.

FTSELL

FTSELR

Port flow through mode select input. Assert this pin LOW to select flow through mode. Assert

this pin HIGH to select Pipelined mode.

MRST

Master reset input. MRST is an asynchronous input signal and affects both ports. Asserting

MRST LOW performs all of the reset functions as described in the text. A MRST operation is

required at power up. This pin is driven by a VDDIOL referenced signal.

TMS

JTAG test mode select input. It controls the advance of JTAG TAP state machine. State

machine transitions occur on the rising edge of TCK. Operation for LVTTL or 2.5 V LVCMOS.

TDI

JTAG test data input. Data on the TDI input is shifted serially into selected registers. Operation

for LVTTL or 2.5 V LVCMOS.

TRST

JTAG reset input. Operation for LVTTL or 2.5 V LVCMOS.

TCK

JTAG test clock input. Operation for LVTTL or 2.5 V LVCMOS.

TDO

JTAG test data output. TDO transitions occur on the falling edge of TCK. TDO is normally

tri-stated except when captured data is shifted out of the JTAG TAP. Operation for LVTTL or 2.5 V

LVCMOS.

VSS

Ground inputs.

VCORE

Device core power supply.

VTTL

LVTTL power supply.

Pin Definitions (continued)

Left Port

Right Port

Description

Note

26. PORTSTD[1:0]L and PORTSTD[1:0]R have internal pull-down resistors.

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