FullFlex

Document Number: 38-06082 Rev. *K

Page 16 of 52

Figure 7. Counter, Mask, and Mirror Logic Block Diagram

Figure 7 shows the counter, mask, and mirror logic block diagram. [32]

Note

32. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and

CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits.

The CYD02S36V18 has 16 address bits.

From

Mask

Register

Mirror

Counter

Address

Decode

RAM

Array

Wrap

1

0

Increment

Logic

1

0

+1

+2

1

0

Wrap

Detect

From

Mask

From

Counter

To Coun-

ter

Bit 0

and 1

Wrap

20

20

20

20

20

1

0

Load/Increment

CNT/MSK

CNTEN

A

CNTRST

C

Decode

Logic

A

Mask

Register

Counter/

Address

Register

From

Address

Lines

To Readback

and Address

Decode

20

20

MRST

RET

+4

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