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FULLFLEX 数据表(PDF) 28 Page - Cypress Semiconductor

部件名 FULLFLEX
功能描述  FullFlex Synchronous SDR Dual Port SRAM Commercial and Industrial temperature
PDF  52 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

FULLFLEX 数据表(HTML) 28 Page - Cypress Semiconductor

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FullFlex
Document Number: 38-06082 Rev. *K
Page 28 of 52
Table 15. Master Reset Timing
Parameter
Description
-200
-167
Unit
Min
Max
Min
Max
tPUP
Power-up time
1
–
1
–
ms
tRS
Master reset pulse width
5
–
5
–
cycles
tRSR
Master reset recovery time
5
–
5
–
cycles
tRSF
Master reset to outputs inactive/Hi Z
–
15
–
18
ns
tRDY[54]
Master reset release to port ready
–
1024
–
1024
cycles
tCORDY[55]
C rise to port ready
–
9.5[56]
–11[56]
ns
Table 16. JTAG Timing
Parameter
Description
-200
-167
Unit
Min
Max
Min
Max
fJTAG
JTAG TAP controller frequency
–
20
–
20
MHz
tTCYC
TCK cycle time
50–50–
ns
tTH
TCK high time
20
–
20
–
ns
tTL
TCK low time
20–20–
ns
tTMSS
TMS setup to TCK rise
10
–
10
–
ns
tTMSH
TMS hold to TCK rise
10–10–
ns
tTDIS
TDI setup to TCK rise
10
–
10
–
ns
tTDIH
TDI hold to TCK rise
10
–
10
–
ns
tTDOV
TCK low to TDO valid
–
10
–
10
ns
tTDOX
TCK low to TDO invalid
0
–
0
–
ns
tJXZ
TCK low to TDO high Z
–
15
–
15
ns
tJZX
TCK low to TDO active
–15–15
ns
tJZX
TCK low to TDO active
–15–15
ns
.
Notes
54. READY is a wired OR capable output with a weak pull-down. For a decreased falling delay, connect a 250-
 resistor to VSS.
55. Add this propagation delay after tRDY for all Master Reset Operations.
56. Add 15% to this parameter if a VCORE of 1.5 V is used.
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