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FULLFLEX 数据表(PDF) 27 Page - Cypress Semiconductor |
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FULLFLEX 数据表(HTML) 27 Page - Cypress Semiconductor |
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27 / 52 page  FullFlex Document Number: 38-06082 Rev. *K Page 27 of 52 tOHZ[50] OE to high Z 1.00 4.40[51, 52] 1.00 5.00[51, 52] ns tCD1 C rise to DQ valid for flow through mode (LowSPD = 0) –9.00[51, 52] – 11.00[51, 52] ns tCA1 C rise to address readback valid for flow through mode – 9.00[52] – 11.00[52] ns tCA2 C rise to address readback valid for pipelined mode – 5.00[52] –6.00[52] ns tDC[53] DQ output hold after C rise 1.00 – 1.00 – ns tJIT Clock input cycle to cycle jitter – +/- 200 – +/- 200 ps tCQHQV[53] Echo clock (CQ) high to output valid HSTL 1.8 V LVCMOS –0.70[51] –0.80[51] ns 2.5 V LVCMOS 3.3 V LVTTL –0.80[51] –0.90[51] ns tCQHQX[53] Echo clock (CQ) high to output hold HSTL 1.8 V LVCMOS –0.70 – –0.80 – ns 2.5 V LVCMOS 3.3 V LVTTL –0.85 – –0.95 – ns tCKHZ1[50] C rise to DQ output high Z in flow through mode 1.00 9.00[51, 52] 1.00 11.00[51, 52] ns tCKLZ1[50] C rise to DQ output low Z in flow through mode 1.00 – 1.00 – ns tAC Address output hold after C rise 1.00 – 1.00 – ns tCKHZA1[50] C rise to address output high Z for flow through mode 1.00 9.00[52] 1.00 11.00[52] ns tCKHZA2[50] C rise to address output high Z for pipelined mode 1.00 5.00[52] 1.00 6.00[52] ns tCKLZA[50] C rise to address output low Z 1.00 – 1.00 – ns tSCINT C rise to CNTINT low 1.00 3.30[52] 1.00 4.00[52] ns tRCINT C rise to CNTINT high 1.00 3.30[52] 1.00 4.00[52] ns tSINT C rise to INT low 0.50 7.00[52] 0.50 8.00[52] ns tRINT C rise to INT high 0.50 7.00[52] 0.50 8.00[52] ns tBSY C rise to BUSY valid 1.00 3.30[52] 1.00 4.00[52] ns Table 14. SDR Mode (continued) Parameter Description -200 -167 Unit Min Max Min Max Notes 50. Parameters specified with the load capacitance in Figure 9 on page 25 and Figure 10 on page 25. 51. For the x18 devices, add 200 ps to this parameter in Table 14. 52. Add 15% to this parameter if a VCORE of 1.5 V is used. 53. This parameter assumes input clock cycle to cycle jitter of ± 0ps. [+] Feedback |
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