FullFlex

Document Number: 38-06082 Rev. *K

Page 17 of 52

Figure 8. Programmable Counter-Mask Register Operation with WRP deasserted

Figure 8 shows the programmable counter-mask operation with WRP deasserted. [36, 38]

Table 8. Interrupt Operation Example

Table 8 shows the interrupt operation example. [33, 34, 35, 37, 38]

Function

Left Port

Right Port

L

L

Max Address

X

X

X

X

L

X

X

X

X

H

L

Max Address

H

X

X

X

L

L

L

Max Address–1

X

H

L

Max Address–1

H

X

X

X

X

H

H

L

H

11

0s

1

0

1

0

1

11

00

Xs

0

X

1

X

0

01

11

Xs

1

X

1

X

1

11

00

Xs

0

X

1

X

0

01

Masked Address

Unmasked Address

Mask

Register

LSB

Address

Counter

LSB

CNTINT

Example:

Load

Counter-Mask

Register = 00007F

Load

Address

Counter = 000005

Max

Address

Value

Max + 1

Address

Value

0

X

X

X

Notes

deasserted after that. Data is out after the following C edge and is tri-stated after the next C edge.

34. OE is “Don’t Care” for mailbox operation.

35. At least one of BE0, BE1, BE2, BE3, BE4, BE5, BE6, or BE7 must be LOW.

36. The “X” in this diagram represents the counter’s upper bits.

37. “X” = Don’t Care, “H” = HIGH, “L” = LOW.

38. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and

CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits.

The CYD02S36V18 has 16 address bits.

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