LSM330DL datasheet(22/54 Pages) STMICROELECTRONICS

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Digital interfaces

LSM330DL

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Doc ID 022018 Rev 1

5.1.1

I2C operation

The transaction on the bus is started through a START (ST) signal. A START condition is

defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After

this has been transmitted by the Master, the bus is considered busy. The next byte of data

transmitted after the start condition contains the address of the slave in the first 7 bits and

the eighth bit tells whether the Master is receiving data from the slave or transmitting data to

the slave. When an address is sent, each device in the system compares the first seven bits

after a start condition with its own address. If they match, the device considers itself

addressed by the Master.

Data transfer with acknowledge is mandatory. The transmitter must release the SDA line

during the acknowledge pulse. The receiver must then pull the data line LOW so that it

remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which

has been addressed is obliged to generate an acknowledge after each byte of data

received.

The I2C embedded inside the LSM330DL behaves like a slave device and the following

protocol must be adhered to. After the start condition (ST) a slave address is sent, once a

slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) will be

transmitted: the 7 LSb represents the actual register address while the MSB enables the

address auto increment. If the MSb of the SUB field is ‘1’, the SUB (register address) will be

automatically increased to allow multiple data read/writes.

Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number

of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit

(MSb) first. If a receiver can’t receive another complete byte of data until it has performed

some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait

Table 12.

Transfer when master is writing one byte to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 13.

Transfer when master is writing multiple bytes to slave

Master

SAD + W

SUB

DATA

Slave

SAK

Table 14.

Transfer when master is receiving (reading) one byte of data from slave

Master

SAD + W

SUB

SAD + R

NMAK

Slave

SAK

DATA

Table 15.

Transfer when master is receiving (reading) multiple bytes of data from slave

Master

ST SAD+W

SUB

SR SAD+R

MAK

NMAK

Slave

SAK

DATA

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