LSM330DL datasheet(39/54 Pages) STMICROELECTRONICS

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LSM330DL

Registers description

Doc ID 022018 Rev 1

39/54

7.24

CTRL_REG1_G (20h)

DR<1:0> is used to set the ODR selection. BW <1:0> is used to set bandwidth selection.

The following table gives the frequencies for all combinations of the DR / BW bits.

Table 63.

CTRL_REG1_G register

DR1

DR0

BW1

BW0

Zen

Yen

Xen

Table 64.

CTRL_REG1_G description

DR1-DR0

Output data rate selection. Refer to

Table 65: DR and BW configuration setting

BW1-BW0

Bandwidth selection. Refer to

Table 65: DR and BW configuration setting

Power-down mode enable. Default value: 0

(0: power-down mode, 1: normal mode or sleep mode)

Zen

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Yen

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

Xen

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

Table 65.

DR and BW configuration setting

DR <1:0>

BW <1:0>

ODR [Hz]

cutoff [Hz]

100

12.5

100

200

12.5

200

400

110

800

110

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