LSM330DL datasheet(47/54 Pages) STMICROELECTRONICS

47 / 54 page

LSM330DL

Registers description

Doc ID 022018 Rev 1

47/54

7.38

INT1_SRC_G (31h)

The interrupt source register is a read-only register.

Reading at this address clears the INT1_SRC_G IA bit (and eventually the interrupt signal

on the INT1_G pin) and allows the refreshment of data in the INT1_SRC_G register if the

latched option was chosen.

7.39

INT1_THS_XH_G (32h)

7.40

INT1_THS_XL_G (33h)

Table 92.

INT1_SRC_G register

0(1)

This bit has to be set to ‘0’ for correct operation.

Table 93.

INT1_SRC_G description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0 (0: no interrupt, 1: X high event has occurred)

X low. Default value: 0 (0: no interrupt, 1: X low event has occurred)

Table 94.

INT1_THS_XH_G register

THSX14

THSX13

THSX12

THSX11

THSX10

THSX9

THSX8

Table 95.

INT1_THS_XH_G description

THSX14 - THSX9

Interrupt threshold. Default value: 0000 0000

Table 96.

INT1_THS_XL_G register

THSX7

THSX6

THSX5

THSX4

THSX3

THSX2

THSX1

THSX0

Table 97.

INT1_THS_XL_G description

THSX7 - THSX0

Interrupt threshold. Default value: 0000 0000

LSM330DL 数据表(PDF) 47 Page - STMicroelectronics

LSM330DL 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载