LSM330DL datasheet(32/54 Pages) STMICROELECTRONICS

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Registers description

LSM330DL

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Doc ID 022018 Rev 1

7.5

CTRL_REG5_A (24h)

7.6

CTRL_REG6_A (25h)

7.7

REFERENCE/DATACAPTURE_A (26h)

Table 30.

CTRL_REG5_A register

BOOT

FIFO_EN

LIR_INT1

D4D_INT1

0(1)

This bit has to be set ‘0’ for correct operation.

0(1)

Table 31.

CTRL_REG5_A description

BOOT

Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN

FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO enable)

LIR_INT1

Latch interrupt request on INT1_SRC_A register, with INT1_SRC_A register

cleared by reading INT1_SRC_A itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

D4D_INT1

4D enable: 4D detection is enabled on INT1_A when 6D bit on INT1_CFG_A

is set to 1.

Table 32.

CTRL_REG6_A register

I2_CLICKen

I2_INT1

0(1)

This bit has to be set to ‘0’ for correct operation.

BOOT_I2

0(1)

H_LACTIVE

Table 33.

CTRL_REG6 description

I2_CLICKen

Click interrupt on INT2_A. Default value 0.

I2_INT1

Interrupt 1 function enabled on INT2_A. Default 0.

BOOT_I2

Boot on INT2_A.

H_LACTIVE

0: interrupt active high; 1: interrupt active low.

Table 34.

REFERENCE/DATACAPTURE_A register

Ref7

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

Ref0

Table 35.

REFERENCE/DATACAPTURE_A register description

Ref 7-Ref0

Reference value for interrupt generation. Default value: 0

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