LSM330DL datasheet(31/54 Pages) STMICROELECTRONICS

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LSM330DL

Registers description

Doc ID 022018 Rev 1

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7.3

CTRL_REG3_A (22h)

7.4

CTRL_REG4_A (23h)

Table 26.

CTRL_REG3_A register

I1_CLICK

I1_AOI1

0(1)

This bit has to be set ‘0’ for correct operation.

I1_DRDY1

I1_DRDY2

I1_WTM

I1_OVERRUN

Table 27.

CTRL_REG3_A description

I1_CLICK

CLICK interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_AOI1

AOI1 interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_DRDY1

DRDY1 interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_DRDY2

DRDY2 interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_WTM

FIFO watermark interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

I1_OVERRUN

FIFO overrun interrupt on INT1_A. Default value 0.

(0: Disable; 1: Enable)

Table 28.

CTRL_REG4_A register

BDU

BLE

FS1

FS0

0(1)

SIM

Table 29.

CTRL_REG4_A description

BDU

Block data update. Default value: 0(0: continuous update; 1: output registers

not updated until MSB and LSB reading)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSB at lower address; 1: Data MSB at lower address)

FS1-FS0

Full-scale selection. default value: 00

(00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G)

Normal mode: default value: 0

(0: normal mode disable; 1: normal mode enable

SIM

SPI serial interface mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface)

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