LSM330DL datasheet(41/54 Pages) STMICROELECTRONICS

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LSM330DL

Registers description

Doc ID 022018 Rev 1

41/54

7.26

CTRL_REG3_G (22h)

7.27

CTRL_REG4_G (23h)

0110

0.1

0.2

0.5

0111

0.05

0.1

0.2

0.5

1000

0.02

0.05

0.1

0.2

1001

0.01

0.02

0.05

0.1

Table 70.

High-pass filter cutoff frequency configuration [Hz] (continued)

HPCF3-0

ODR = 100 Hz

ODR = 200 Hz

ODR = 400 Hz

ODR = 800 Hz

Table 71.

CTRL_REG3_G register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 72.

CTRL_REG3_G description

I1_Int1

Interrupt enable on INT1_G pin. Default value 0. (0: Disable; 1: Enable)

I1_Boot

Boot status available on INT1_G. Default value 0. (0: Disable; 1: Enable)

H_Lactive

Interrupt active configuration on INT1_G. Default value 0. (0: High; 1:Low)

PP_OD

Push-Pull / Open drain. Default value: 0. (0: Push-Pull; 1: Open drain)

I2_DRDY

Date Ready on DRDY_G/INT2_G. Default value 0. (0: Disable; 1: Enable)

I2_WTM

FIFO watermark interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable)

I2_ORun

FIFO overrun interrupt on DRDY_G/INT2_G Default value: 0. (0: Disable; 1: Enable)

I2_Empty

FIFO empty interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable)

Table 73.

CTRL_REG4_G register

BDU

BLE

FS1

FS0

0(1)

This bit has to be set to ‘0’ for correct operation.

0(1)

SIM

Table 74.

CTRL_REG4_G description

BDU

Block data update. Default value: 0

(0: continuous update; 1: output registers not updated until MSB and LSB

have been read)

BLE

Big/little endian data selection. Default value 0.

(0: Data LSB at lower address; 1: Data MSB at lower address)

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